The STM32 interrupt process is as follows:

Write the external interrupt configuration according to the flow

①Initialize the IO port as input

GPIOE_CRL &= ~(0XF << 16);
GPIOE_CRL |= 0x8 << 16;// Set PE4 up and down input mode 2MHZ
GPIOE->ODR|=1<<4;	   	//PE4 pull-up 

②Open the IO port multiplexing clock

RCC->APB2ENR |= 1<<6; // Enable APB2 bus clock
RCC->APB2ENR|=0x01;//Enable io multiplexed clock	

③Set the mapping relationship between the IO port and the interrupt line

AFIO->EXTICR[1] &= 0xfff0; 
AFIO->EXTICR[1] |= 0xfff4; // PE4 is configured as external interrupt 4

④Initialize online interrupts, set trigger conditions, etc.

EXTI->IMR |= 1<<4; // Let go of the interrupt from line 4
EXTI->FTSR |= 1<<4; // Enable interrupt on falling edge of line 4

⑤ Configure interrupt grouping (NVIC) and enable interrupt

temp = SCB->AIRCR; // read previous value
temp &= 0X0000F8FF;  // Clear the high bit and set 0 to BIT[10:8]
temp |= (0X05FA<<16 | (7 - group) << 8);  // Set the secret key and set the priority grouping
SCB->AIRCR = temp;

NVIC->ISER[interrupt_channel/32] |= (1<<(interrupt_channel%32)); // Enable EXIT4 interrupt bit interrupt_channel is the interrupt channel number in the interrupt table
NVIC->IP[interrupt_channel] = priority << 4;  //IPn[7:4] indicates the priority: if the current interrupt priority priority =0x7 (0111, it means preemption 3, response 1)

⑥ Write interrupt service function

//External Interrupt 4 Service Routine
void EXTI4_IRQHandler(void)
{
	unsigned char i = 0;
	delay_ms(10);	//Debounce
	if(KEY0==0)	 	//button KEY0
	{
		for(;i<5;i++) {
			BEEP=1;
			LED_RED = ~LED_RED;
			delay_ms(100);
			BEEP=0;
			LED_RED = ~LED_RED;
			delay_ms(100);
		}
	}		 
	EXIT1->PR=1<<4;  //Clear the interrupt flag bit on LINE4  
}	

⑦Clear the interrupt flag bit

EXIT1->PR=1<<4;  //Clear the interrupt flag bit on LINE4

illustrate

1. Why choose AFIO->EXTICR[1] in step 3?

Because our button is on the PE4 pin, the 4 pin corresponds to the interrupt.

2. In step 5, set the enable of NIVC_ISER[?] to the corresponding channel interrupt number, then ? What is the index of this array? See M3's manual ISER register introduction

So confirm here according to the corresponding terminal number? What is it (for example the terminal number for external interrupt 4 EXIT4 is 10, which is in 0-31, so ?=0). ISER is a register used to control the enable of NVIC interrupts.

1. Set interrupted grouping via SCB->AIRCR
   
   
   Looking at the AIRCR register, people ask to write the key and set the grouping through ARICR[10:8]
   
   Set the interrupt priority grouping in Bit[10:8] of this register

1. If the priority group is set to 4:

The current interrupt can only set the preemption priority (0 ~ 15), no response priority can be set

1. If the priority group is set to 3:

The current interrupt can be set to preemption level (0~7) + response can be set to (0~1)

1. If the priority group is set to 2:

Current interrupt can be set to preemptive level (0 ~ 3) Response can be set to (0 ~ 3)

1. If the priority group is set to 1:

Current interrupt can be set to preemptive level (0 ~ 1) Response can be set to (0 ~ 7)

1. If the priority group is set to 0:

No preemption priority can be set for the current interrupt, and the response priority can be set (0 ~ 15)

The priority is set, and NVIC->IP[7:4] is assigned a value through a hexadecimal identifier.

Knowing this, look at

temp = SCB->AIRCR; // read previous value
temp &= 0X0000F8FF;  // Clear the high bit and set 0 to BIT[10:8]
temp |= (0X05FA<<16 | (7 - group) << 8);  // Set the secret key and set the priority grouping
SCB->AIRCR = temp;

NVIC->ISER[interrupt_channel/32] |= (1<<(interrupt_channel%32)); // Enable EXIT4 interrupt bit interrupt_channel is the interrupt channel number in the interrupt table
NVIC->IP[interrupt_channel] = priority << 4;  //IPn[7:4] indicates the priority: if the current interrupt priority priority =0x7 (0111, it means preemption 3, response 1)

Simple.

refer to:

STM32 interrupt management

ST's cortex-m3 core description

STM32 Chinese manual